Memory cell array with multiplexed column select lines

ABSTRACT

The invention relates to memory-cell arrays wherein the COLUMN SELECT lines are multiplexed so that for, say, the nth cell, the COLUMN SELECT lines associated with the (n-1) and (n+1) cells function as the BIT and BIT lines for the nth cell. Means for reading and writing into the cells of this array are also disclosed.

4 United States Patent 1 1 3,800,299 Panther Mar. 26, 1974 MEMORY CELL ARRAY WITH 3,541,531 11/1970 Iwersen et a1. 340/173 FF MULTIPLEXED COLUMN SELECT LINES 3,641,51 1 2/1972 Cricchi et al. 340/173 FF 3,651,491 3/1972 Kobayashi 340/173 FF [75] Inventor: Gyles Panther, Ottawa, Ontario,

I Canada Primary Examiner-Bernard Konick [73] Assigneez Microsystems International Limited, Assistant Examiner stuart Becker Quebec Canada Attorney, Agent, or FirmE. E. Pascal [22] Filed: Feb. 6, 1973 [21] Appl. No.: 329,994 7 ABSTRACT [30] Foreign Application Priority Data The invention relates to memory-cell arrays wherein Dec. 22, 1972 Canada the COLUMN SELECT lines are multiplexed so that 52 us. c1.'. 340/173 FF, 307/241 for, Say, the nth cell, the COLUMN SELECT lines 51 Int. Cl .Gllc 7/00, 6110 11/40 sedated Wit1 1 the and cells function s [58] Field of Search 340/173 FF 173 the BIT and BIT lines for the nth cell. Means for read- 307/241, 238 ng and writing into the cells of this array are also disclosed.

[56] References Cited UNITED STATES PATENTS 6 Clam, 6 Draw 3,328,769 6/1967 Lee 340/173 FF (n-4) (n-3) (n-2) (n-ll n (n+1) (n+2) (n+3) (n+4) 01-41 01-3) 01-21 0 -1) n 01 11 W2) 0031 (n+4) I O O l O l I O l I O I O 1 b h I (n-4) (n-3) Mn-2'1 11 41 n (n+l) 111 2) n +31 111 4) PAIENIEUMms I974 sum 2 BF 3 3800299 PAIENTEUmes am 3800 299 SHEEI 3 0F 3 I QIG MEMORY CELL ARRAY WITH MULTIPLEXED COLUMN SELECT LINES The present invention relates to memory-cell arrays.

A memory-cell array conventionally comprises a network of parallel BIT, COLUMN SELECT and BTT rails extending in one direction and parallel power supply and 4 where more than one row of cells is used @W SELECT rails extending at 90 to the BIT and BIT rails. Memory cells are connected between the rails in an array. To determine the state of a cell, the cell is powered by applying potential thereto through the COLUMN SELECT rail associated with that cell by the term applying potential thereto, it is meant that the impedance to ground of the COLUMN SE- LECT rail is modified so that current preferentially flows from the power supply rail into the BIT or BIT rail, or the COLUMN SELECT rail itself may become the power supply for the cell and the associated BIT and BIT rails are sensed to determine which side of the cell has a .ONE" information stored therein and viceversa. It is understood that throughout this application, a ONE logic level indicates an enabling potential level for devices in the circuit and a ZERO a disabling potential.

A conventional array of this type has a number of disadvantages particularly when fabricated in integrated circuit form. A large numer of connections are needed as well as underpasses and cross-overs upon the chip because of the large number of rails involved. The purpose of the present invention is to eliminate some of these rails specifically the BIT and B IT rails by multiplexing the COLUMN SELECT rail functions. In this manner, the number of underpasses and connectionsrequired are reduced considerably.

Thus, according to the present invention, I provide a binary logic memory array having a plurality of memory cells, each of said cells having first, second and third COLUMN SELECT lines associated therewith, said first and third lines connected to first and second complementary level output terminals of each said cell and said second line connected to each said cell for applying a potential to that cell such that an output is derived from one or other of said complementary output terminals thereof indicative of the logic state of said cell; the improvement comprising means for connection to a potential supply means for selectively applying a potential to the nth cell in said array through the COLUMN (n) SELECT line associated therewith -r the integer (n) referencing any given cell and its associated COLUMN SELECT line with respect to which the remaining said cells and COLUMN SELECT lines are referenced such that an output potential indicative of the logic state of said cell appears as aforesaid on the adjacent COLUMN (n-l) SELECT line or COLUMN (n+1) SELECT line and means for reading the logic state of said cell by sensing the relative potential levels of said COLUMN (n1) SELECT line and said COLUMN (n+1) SELECT line and for writing information into said cell by modifying the potential lev- -els of said COLUMN (n-l) SELECT line and said COLUMN (n+1) SELECT line in order to change the logic state of said cell.

The invention will now be described further by way of example only and with reference to the accompanying drawings in which:

FIG. 1 shows in block form a cell connected into a memory array in the manner of the prior art;

FIG. 2 shows part of a memory-cell array according to the present invention;

FIG. 3 shows part ofa read/write circuit for use in the memory-cell array of the present invention;

FIGS. 4 and 5 show peripheral circuitry for use with the circuit of FIG. 3; and

FIG. 6 shows a specific embodiment of the circuit of FIG. 3.

The memory array is comprised of cells having binary complementary outputs. Many different kinds of cell configurations have such output properties, the great majority of which are based on the well-known flipflop. FIG. I of the drawings shows one type of cell which is widely in use in conventional memory cell arrays, and such cell is readily adaptable for use in the array of the present invention. Referring to FIG. 1, there is shown a typical memory cell comprising transistors l0 and 12, each having three emitter electrodes 20a, 20b and 20c and 22a, 22b and 220, respectively. The bases of transistors 10 and 12 are cross-coupled with their opposite collector electrodes and the collector electrodes are connected to a V supply rail through resistors 30 and 32. Emitters 20a and 22a are connected to BIT and W rails B and B, respectively, emitters 20b and 22b are connected to a ROW SE- LECT rail RS and emitters 20c and 22c are connected to a COLUMN SELECT rail CS. Since transistors 10 and 12 constitute, in combination, a flip-flop, when one transistor is enabled, the other is disabled. In the quiescent state of the cell, current is drawn from the V rail,

, through whichever transistor is enabled, into the COL- UMN SELECT rail. To determine the state of the memory cell and obtain a readout therefrom, the impedances to ground of the ROW SELECT and COL- UMN SELECT rails are raised so that an output will be derived at emitter 20a, feeding the BIT line, if transistor 10 is enabled or at emitter 22a, feeding the BTT line, if transistor 12 is enabled.

Connecting the cell of FIG. 1 into a conventional memory-cell array has a serious disadvantage, particularly when the array is fabricated in integrated-circuit form and that is that an undesirably large number of connections is required. Since the V, rail is shared by mirror-image rows of cells and the BIT and Bi rails by adjacent columns, these may be said to constitute three half-connections. Connections are also required for the ROW SELECT and COLUMN SELECT rails. Now, it may be seen that the V and ROW SELECT rails cross paths with the BIT and IT rails and with single-layer integrated circuit technology, both the former rails require diffused underpasses beneath the BIT and BIT rails. This problem could be diminished to some extent by making the V rail parallel to the BIT and BTT rails. Now, only the ROW SELECT rail would cross paths with the BIT and BTT rails. However, the rail can no longer be shared in this configuration and the total number of connections on the chip is therefore increased. Thus, one improvement must be traded-off against a deterioration in chip real-estate u tilization.

In the present invention, the BIT and BIT lines are replaced by the COLUMN SELECT lines of the adjacent cells. If the cell of FIG. 1 is now considered to be the nth cell in a row of a memory array, the emitters 20c and 220 are connected to the COLUMN (n) SE- LECT rail, the emitters 20b and 22b are connected to the ROW SELECT rail and now, instead of being connected to the BIT and W rails, the emitters 20c and 22c are connected to the COLUMN (nl) SELECT and COLUMN (n+1) SELECT rails, respectively.

To read the cell, a read/write network attached to the memory-cell array connects the COLUMN (nl) SE LECT and COLUMN (n+1) SELECT rails to reference ground potential through a relatively low impedance. Now, current from whichever side of the cell is at level ZERO is drained through either the COLUMN (n+1) SELECT or COLUMN (nl) SELECT rails and by sensing which rail carries such current, the state of the cell may be read. To write into the cell and change its state, the side having the ONE level is connected through the appropriate COLUMN (nl) SELECT or COLUMN (n+1) SELECT rail and a low impedance means to reference ground potential. Now, this side of the cell goes to ZERO level and, since the cell is complementary, the other side goes to ONE.

As stated above, the cell of FIG. I is typical of the type of cell which may be used in the array of the present invention. An improvement upon the cell of FIG. I would be means to take advantage of the relatively high potential to which the (n) rail may be raised for reading of the cell by drawing current from the (n) rail during the READ operation and using a relatively low current draw from the V rail during the quiescent state of the cell. Such means may conveniently take the form of a series diode/resistor connection between each of the collectors of transistors and 12 and the (n) rail. The diodes prevent pull-clown of the transistor bases when the (n) rail goes to ZERO.

FIG. 2 shows part of a memory array according to the present invention having a row of memory cell designated from C to C inclusive and COLUMN SE- LECT rails designated (n4) to (n+4) inclusive associated therewith. For clarity, the ROW SELECT and VR rails of FIG. 1 are omitted. Each COLUMN SE- LECT rail terminates in a sense/drive module M,,, M,,, M respectively, the modules comprising, in combination, a complete read/write circuit for the array. Associated with the module M e. is a connection to a SENSE rail S, and a connection to a WRITE rail W,. Associated with the module M is a connection to the line S, and to the line W,. Associated with the module M is a connection to a SENSE rail S and a WRITE rail W Associated with the module M,,, is a connection to line 8,, and line W,,. Thus, it will be seen that the SENSE line and WRITE rail connections go in pairs, i.e., one pair of modules feeds the S, and W, lines, the next pair feeds the S and W lines, the next pair feeds the S, and W, lines, and so on. Suppose the cells have information stored therein as shown in FIG. 2. As explained in connection with FIG. 1, current is drawn from whichever side of the cell is at ZERO, through the COLUMN SELECT line associated therewith. So, ifC 4) is read by raising the (n) rail, current is drawn down the (rt-3) rail. Each module is such that current will flow in the SENSE rail to which that module is connected if a current flows in the associated COLUMN SELECT rail. Therefore, when current flows down the (n3) rail, current will also flow in the S, rail. When C,,,.,,, is read, current flows in the (n4) rail and, therefore, again in the S, rail.

It may be seen that, going through the cells in sequence, current always flows in the S, rail and thus, for a logic ONE output throughout the array the states of the cells are as shown in FIG. 2, i.e.,' l, 0; 0, l; 0, l; l, O; l, 0 etc. To write into a cell, say C,,, we raise the impedance to ground of the W, and (n) rails and we lower the impedance to ground of the WRITE ZERO rail W The modules M and M function as will hereinafter be described to effectively clamp the (nl) and (n+1) rails to the W and W, rails, respectively. Now the complementary outputs of the cell C,, change to (l, 1. If the array is now read through again, each cell will show a ONE output as current flows in the S, rail, except for cell C,,. When this cell is read, the side now having the ZERO level is that associated with the (nl) rail. Thus, when this cell is read, current flows in the S rail, indicating the ZERO condition of this cell.

FIG. 3 shows a circuit for reading and writing into a cell as described in FIG. 1. 'Ihe COLUMN (nl) SE- LECT, COLUMN (n) SELECT and COLUMN (n+1)- SELECT rails are again shown and are again designated (nl), (n) and (n+1 respectively. To the left of the COLUMN (nl) SELECT rail in the drawing are the rails (n2), (n3) etc. (not shown) and to the right of the COLUMN (n+1) SELECT rail in the drawing are the rails (n+2), (n+3) etc. (not shown). Running at to the COLUMN SELECT rails are a voltage supply rail V,; SENSE 0" and SENSE l rails S and 8,, respectively; a READ rail RR; and WRITE 0" and WRITE l rails W and W,, respectively. Each of the SENSE O and SENSE l rails has means associated therewith (not shown in FIG. 3) for sensing the current flow therein and each of the READ, WRITE O and WRITE l rails has means (not shown in FIG. 3) for selectively connecting the rail through either a low or high impedance to reference ground potential. Each of the COLUMN (nl) SELECT, COLUMN (n) SE- LECT and COLUMN (nl) SELECT rails is selectively connected to the voltage supply rail V, through a transistor Q,,, O or Q respectively. The transistors 0,,, 0, and O have their control electrodes connected through rails L,,, L, and L,,, to selection means (not shown) for selecting which COLUMN SELECT rail is to be powered.

Associated with the COLUMN (n+1) SELECT rail are transistors Q,,, Q, and Q The control electrodes of these transistors are interconnected and connected through series connected diode D, and resistor R, to the COLUMN (n) SELECT rail. The control electrodes of Q,,, Q, and 0 are also connected through series connected diode D and resistor R to the COL- UMN (n+2) SELECT rail. The COLUMN (n+1) SE- LECT rail is connected to the READ rail RR through transistor Q, and to the WRITE I rail W, through transistor 0 The SENSE l rail S, is connected to the READ rail RR through transistor Q Associated with the COLUMN (n) SELECT rail are transistors Q Q and Q The control electrodes of these transistors are interconnected and connected through series connected diode D and resistor R to the COLUMN (nl) SELECT rail. The control electrodes of Q Q and O are also connected through series connected diode D, and resistor R to the COL- UMN (n+1) SELECT rail. The COLUMN (n) SE- LECT rail is connected to the READ rail RR through transistor Q and to the WRITE 0 rail W through transistor 0,. The SENSE 0 rail 8,, is connected to the READ rail RR through transistor Q Associated with the COLUMN (nl) SELECT rail are transistors Q5, Q3 and Q The control electrodes of these transistors are interconnected and connected through series connected diode D and resistor R to the COLUMN (n) SELECT rail. The control electrodes of Q Q and O, are also connected through a similar series diode resistor path to the COLUMN (n2) SELECT rail (not shown). The COLUMN (nl) SELECT rail is connected to the READ rail RR through transistor and to the WRITE 0 rail W,, through transistor The SENSE 0 rail S is connected to the READ rail RR through transistor 0,.

The circuit operates as follows. To read, say, the cell associated with the COLUMN (n) SELECT rail, the power is applied to this rail from the V, rail by enabling transistor Q, via line L, Now, transistors, 0 0,, and Q have enabling potential applied to their control electrodes through resistor R and diode D Similarly, enabling potential is applied to the control electrodes of transistors Q,,, Q, and Q through resistor R, and diode D,. When the cell is being read, the impedance of the READ rail RR to reference ground potential is low and the impedances of the WRITE rails W,, and W, are high. Assuming, now, that the state of the cell being read is such that it is storing a ONE at its side associated with the COLUMN (nl) SELECT rail and a ZERO at its side associated with the COLUMN (n+1) SELECT rail. Now, relatively high current will flow from the cell down the (n+1) rail whereas relatively little or no current will flow down the (nl rail. Transistor Q and 0 are arranged to be a matched pair in terms of their current drawing properties, so that whatever current is drawn through 0 substantially the same current will be passed by 0,. Thus, Q may be said to mirror the current draw through Q Similarly, transistors Q, and Q constitute a matched pair and Q mirrors the current draw through Q,. Since much higher current is drawn from the (n+1) line through 0, than is drawn from the (n-1) line through Q the current draw through Q will be correspondingly higher than that through 0,. Thus the current drawn from the SENSE l line S, will be much higher than that drawn from the SENSE 0 line S and this current draw may be sensed. Thus the condition of the cell is readily observable.

The means for sensing the current flow through each oflines S and S, may be any current sensing means well known to those skilled in the art. For the present application, a convenient form of sensing means is shown in FIG. 4. The SENSE lines S and S, are connected through transistors 0, and 0, and resistors R and R respectively, to the voltage supply rail VR. The control electrodes of Q,,, and Q, are interconnected and connected to a bias potential input terminal B. Thus, Q14 and 0, are biased to the same potential and if outputs from the memory array are tapped from the junctions of the resistor R and Q14 and of the resistor R and Q these outputs will reflect the current drawn through these resistors from the voltage supply rail VR. Thus, the outputs of the array are directly dependent upon the respective current draws in the S and S, lines which are in direct correspondence to the state of the cell being read.

Returning to FIG. 3, to write into the cell, the impedance of the READ rail RR to ground is raised and the impedance of the appropriate WRITE line is lowered. Thus, if it is desired to write a ONE into the side of the cell associated with the COLUMN (nl) SELECT rail,

the impedance of the W, rail is left high and that of the W rail is lowered. Now, there is a high impedance to reference ground potential from the (n+1) raiI since both the RR and W, rails are presenting high impedance, and, therefore the output node of the cell associated with the (n+1) rail goes to level ONE. SInce the outputs of the cell are complementary, and since there is a low impedance path to current flowing down the (nI) rail and through transistor Q and the W line to reference ground potential, the output node of the cell associated with the (nl) rail goes to level ZERO.

The means for selectively changing the impedance of each of the READ and WRITE rails are conventional and, as shown in FIG. 5, typically comprises a low value resistor R,., and a transistor O in series therewith between the rail and a reference ground potential point, so that when the transistor is disabled, a high impedance path exists and when it is enabled, a low impedance path exists, the transistor being controlled by appropriate selection means (not shown) connected to its control electrode. Various alternative means for achieving similar effect will, of course, be apparent to those skilled in the art.

FIG. 6 shows one embodiment of the invention using bipolar transistors. The circuit comprises a series of parallel COLUMN SELECT rails designated (n-l (n), (n+1) etc., as in FIG. 2. Each rail may be fed current from a V rail through Darlington pairs T,,,,, T,,,,, the base of each transistor T,,,, being selectively powered by peripheral circuitry (not shown) through a rail L,,, L, or L, Thus if the COLUMN (n) SELECT rail is to be powered, the transistor T,,,, associated with that rail is enabled through the rail L, Connected to each COLUMN SELECT rail is the collector of a transistor T T or T,, respectively. Each such transistor has two emitters, the first of which is connected to a READ rail RR, the second emitter of each of T and T is connected to a WRITE 0" rail W and the second emitter of T, is connected to a WRITE l rail W,. Transistors T and T are connected between the READ rail RR and a SENSE 0 rail S and a transistor T is connected between the rail RR and a SENSE l rail 8,. The bases of T and T are interconnected and connected through diode D and resistor R to the COL UMN (n) SELECT rail and also through a series diode/resistor path to the COLUMN (rt-2) SELECT rail (not shown). The bases of T,, and T are interconnected and connected through a diode D and a resistor R to the COLUMN (nl) SELECT rail and also through a diode D and a resistor R to the COLUMN (n+1) SE- LECT rail. The bases of T, and T are interconnected and connected through a diode D, and resistor R, to the COLUMN (n) SELECT rail and also through a similar series diode/resistor path to the COLUMN (n+2) SELECT rail (not shown).

The operation of the circuit is as follows. Suppose the side of the cell delivering current is that connected to the COLUMN (n+1) SELECT rail, This indicates a ZERO condition on that side of the cell. In order to keep the cell in this condition, a low impedance must be presented to the current flow down the COLUMN (n+1) SELECT rail. The low impedance is constituted by transistor T,, which sinks the current to the READ rail RR..The transistor T, is enabled by potential de rived from the COLUMNtn) SELECT rail through resistor R, and diode D,. The transistor T mirrors" the current flow through T, and, since this current is relatively high, a high current flows in the SENSE l rail S The base of transistor T is connected to the COL- UMN (n) SELECT rail through resistor R and diode D and is therefore enabled thereby. However, relatively low current flows down the COLUMN (n-l) SE- LECT rail and this is mirrored by transistor T Thus very low current flows in the SENSE rail S Thus, by observing the current flows in the two SENSE rails, the state of the cell may be read as described above. As before, during the READ" operation, the WRITE rails are connected through a high impedance to reference ground potential in order that substantially no current flows into such rails from T and T To write into the cell, the impedance of the READ rail is raised so that no current flows into the rail from transistors T and T The side of the cell associated with the COLUMN (n+1) SELECT rail is presently at a ZERO level. To write a ONE into this side of the cell, the WRITE 1 rail remains at its previous high impedance level, the WRITE O rail now showing a low impedance. Now, a high impedance is presented to the ZERO output from the cell and this forces the state of the cell to reverse, as in the manner described above.

The transistors T T and T are shown in FIG. 6 as clamping transistors. These are preferable from the viewpoint of speed a technique well-known in Schottky TTL technology. However, the use of such transistors is by no means mandatory and, indeed, by appropriate circuit and potential level revisions, fieldeffect transistors may well be used throughout, instead of bipolar transistors. The use of the diode/resistor paths to provide enabling potentials to the transistors is for the purpose of potential level matching and is again a well-known technique.

Various alternatives and modifications to the embodiments disclosed herein will be readily apparent to those skilled in the art without departing from the spirit and scope of the invention as described by the disclosure and defined by the claims appended hereto.

What is claimed is:

l. A binary logic memory array having a plurality of memory cells, each of said cells having first, second and third COLUMN SELECT lines associated therewith, said first and third lines connected to first and second complementary level output terminals of each said cell and said second line connected to each said cell for applying a potential to that cell such that an output is derived from one or other of said complementary output terminals thereof indicative of the logic state of said cell; the improvement comprising means for connection to a potential supply means for selectively applying a potential to the nth cell in said array through the COLUMN (n) SELECT line associated therewith the integer (n) referencing any given cell and its associated COLUMN SELECT line with respect to which the remaining said cells and COLUMN SELECT lines are referenced such that an output potential indicative of the logic state of said cell appears as aforesaid on the adjacent COLUMN (n-l) SELECT line or COLUMN (n+1) SELECT line and means for reading the logic state of said cell by sensing the relative potential levels of said COLUMN (n-1) SELECT line and said COLUMN (n+1) SELECT line and for writing information into said cell by modifying the potential levels of said COLUMN (n1) SELECT line and said COLUMN (n+1) SELECT line in order to change the logic state of said cell.

2. In a binary logic memory array having a plurality of memory cells, each of said cells having first, second and third COLUMN SELECT lines associated therewith, said first and third lines connected to first and second complementary level output terminals of each said cell and said second line connected to each said cell for applying a potential to that cell such that an output is derived from one or other of said complementary output terminals thereof indicative of the logic state of said cell, the improvement comprising means for connection to a potential supply means for selectively applying a potential to the nth cell in said array through the COLUMN (n) SELECT line associated therewith the integer (n) referencing any given cell and its associated COLUMN SELECT line with respect to which the remaining said cells and COLUMN SE- LECT lines are referenced such that an output potential indicative of the logic state of said cell appears as aforesaid on the adjacent COLUMN (n-l) or COL- UMN (n+1) SELECT line, said COLUMN (n+1) SE- LECT line being connected through first transistor means to a READ line connected through a selected one of either a low or a high impedance means to means for connection to a reference ground potential, said first transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line, second transistor means connected between a first logic level SENSE line and said READ line, said second transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line and having current passing properties substantially the same as those of said first transistor means so that a given current draw through said first transistor means results in a similar current draw through said second transistor means, said COLUMN (nl) SELECT line being connected to said READ line through third transistor means having a control electrode deriving enabling potential from said COL- UMN (n) SELECT line, fourth transistor means connected between a second logic level SENSE line and said READ line, said fourth transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line and having current passing properties substantially the same as those of said third transistor means so that a given current draw through said third transistor means results in a similar current draw through said fourth transistor means, and means for sensing the respective current draws through said second and fourth transistor means from said first and second logic level SENSE lines.

3. The combination of claim 2 wherein each of said transistor means is a bipolar transistor.

4. The combination of claim 2 further comprising means for writing binary logic information into the cell, said means comprising fifth and sixth transistor means, deriving enabling potential from said COLUMN (n) SELECT line, said fifth transistor means connected between said COLUMN (n-l) SELECT line and a first logic level WRITE line connected through a selected one of either a low or high impedance means to means for connection to a reference ground potential and said sixth transistor means connected between said COL- UMN (n+1) SELECT line and a second logic level WRITE line connected through a selected one of either a low or high impedance means to means for connection to a reference ground potential, and control means for selecting the high or low impedance state of said connection between each of said WRITE and READ lines and said means for connection to said reference ground potential, said control means selecting a high impedance state for said connection to said READ line when a low impedance state is selected for either of said connections to said WRITE lines, said control means selecting a high impedance state for both said connections to said WRITE lines when a low impedance state is selected for said connection to said READ line.

5. The combination of claim 4 wherein each of said transistor means is a bipolar transistor.

6. The combination of claim 4 wherein said first and sixth transistors means comprise, in combination, a first transistor having collector, base and first and second emitter electrodes, said collector electrode connected to said COLUMN (nl) SELECT line, said base electrode connected through impedance matching means to said COLUMN (n) SELECT line, said first emitter electrode connected to said READ line and said second emitter electrode connected to said second logic level WRITE line, said second transistor means being a second bipolar transistor and the current passing properties of said first and second transistors being substantially the same; and

said third and fifth transistor means comprise, in combination, a third transistor having collector, base and first and second emitter electrodes, said collector electrode connected to said COLUMN (n+1) SELECT line, said base electrode connected through impedance matching means to said COL- UMN (n) SELECT line, said first emitter electrode connected to said READ line and said second emitter electrode connected to said first logic level WRITE line, said fourth transistor means being a fourth bipolar transistor and the current passing properties of said third and fourth transistors being substantially the same. 

1. A binary logic memory array having a plurality of memory cells, each of said cells having first, second and third COLUMN SELECT lines associated therewith, said first and third lines connected to first and second complementary level output terminals of each said cell and said second line connected to each said cell for applying a potential to that cell such that an output is derived from one or other of said complementary output terminals thereof indicative of the logic state of said cell; the improvement comprising means for connection to a potential supply means for selectively applying a potential to the nth cell in said array through the COLUMN (n) SELECT line associated therewith - the integeR (n) referencing any given cell and its associated COLUMN SELECT line with respect to which the remaining said cells and COLUMN SELECT lines are referenced - such that an output potential indicative of the logic state of said cell appears as aforesaid on the adjacent COLUMN (n-1) SELECT line or COLUMN (n+1) SELECT line and means for reading the logic state of said cell by sensing the relative potential levels of said COLUMN (n-1) SELECT line and said COLUMN (n+1) SELECT line and for writing information into said cell by modifying the potential levels of said COLUMN (n-1) SELECT line and said COLUMN (n+1) SELECT line in order to change the logic state of said cell.
 2. In a binary logic memory array having a plurality of memory cells, each of said cells having first, second and third COLUMN SELECT lines associated therewith, said first and third lines connected to first and second complementary level output terminals of each said cell and said second line connected to each said cell for applying a potential to that cell such that an output is derived from one or other of said complementary output terminals thereof indicative of the logic state of said cell; the improvement comprising means for connection to a potential supply means for selectively applying a potential to the nth cell in said array through the COLUMN (n) SELECT line associated therewith - the integer (n) referencing any given cell and its associated COLUMN SELECT line with respect to which the remaining said cells and COLUMN SELECT lines are referenced - such that an output potential indicative of the logic state of said cell appears as aforesaid on the adjacent COLUMN (n-1) or COLUMN (n+1) SELECT line, said COLUMN (n+1) SELECT line being connected through first transistor means to a READ line connected through a selected one of either a low or a high impedance means to means for connection to a reference ground potential, said first transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line, second transistor means connected between a first logic level SENSE line and said READ line, said second transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line and having current passing properties substantially the same as those of said first transistor means so that a given current draw through said first transistor means results in a similar current draw through said second transistor means, said COLUMN (n-1) SELECT line being connected to said READ line through third transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line, fourth transistor means connected between a second logic level SENSE line and said READ line, said fourth transistor means having a control electrode deriving enabling potential from said COLUMN (n) SELECT line and having current passing properties substantially the same as those of said third transistor means so that a given current draw through said third transistor means results in a similar current draw through said fourth transistor means, and means for sensing the respective current draws through said second and fourth transistor means from said first and second logic level SENSE lines.
 3. The combination of claim 2 wherein each of said transistor means is a bipolar transistor.
 4. The combination of claim 2 further comprising means for writing binary logic information into the cell, said means comprising fifth and sixth transistor means, deriving enabling potential from said COLUMN (n) SELECT line, said fifth transistor means connected between said COLUMN (n-1) SELECT line and a first logic level WRITE line connected through a selected one of either a low or high impedance means to means for coNnection to a reference ground potential and said sixth transistor means connected between said COLUMN (n+1) SELECT line and a second logic level WRITE line connected through a selected one of either a low or high impedance means to means for connection to a reference ground potential, and control means for selecting the high or low impedance state of said connection between each of said WRITE and READ lines and said means for connection to said reference ground potential, said control means selecting a high impedance state for said connection to said READ line when a low impedance state is selected for either of said connections to said WRITE lines, said control means selecting a high impedance state for both said connections to said WRITE lines when a low impedance state is selected for said connection to said READ line.
 5. The combination of claim 4 wherein each of said transistor means is a bipolar transistor.
 6. The combination of claim 4 wherein said first and sixth transistors means comprise, in combination, a first transistor having collector, base and first and second emitter electrodes, said collector electrode connected to said COLUMN (n-1) SELECT line, said base electrode connected through impedance matching means to said COLUMN (n) SELECT line, said first emitter electrode connected to said READ line and said second emitter electrode connected to said second logic level WRITE line, said second transistor means being a second bipolar transistor and the current passing properties of said first and second transistors being substantially the same; and said third and fifth transistor means comprise, in combination, a third transistor having collector, base and first and second emitter electrodes, said collector electrode connected to said COLUMN (n+1) SELECT line, said base electrode connected through impedance matching means to said COLUMN (n) SELECT line, said first emitter electrode connected to said READ line and said second emitter electrode connected to said first logic level WRITE line, said fourth transistor means being a fourth bipolar transistor and the current passing properties of said third and fourth transistors being substantially the same. 